Elements having negative differential resistance are required in semiconductor integrated circuits. As with other active elements, such a negative resistance element of course becomes more attractive with the element's ability to operate at lower voltage and operate at higher speed (with better high-frequency characteristics) and, as such, has been a subject of various studies in the past.
Although a so-called two-terminal element having no control terminal exists, the lack of a control terminal itself tends to be a drawback, limiting control from the outside and usually making the element unsuitable for application as a logic element and as an integrated element. Naturally, no amplification capability or the like can be anticipated. Therefore, a need is, after all, felt for a negative resistance element having a three-terminal structure including at least a control terminal. This assumes, however, what will no doubt continue to be most emphasized as a future trend will be realization of low-voltage operation and a high PVCR.
One response to this has been the proposal of a configuration using a compound heterojunction structure utilizing a high-mobility layer portion whose energy band gap is relatively narrow as the main transit channel for electrons and providing as a second channel in contact with this a low-mobility layer portion with a relatively wide energy band gap (e.g., Reference 1: “Enhanced Resonant Tunneling Real-Space Transfer in delta-Doped GaAs/InGaAs Gated Dual-Channel Transistors Grown by MOCVD”, Chang-Luen Wu et al., IEEE Transactions on Electron Devices, vol. 43, No. 2 (1996) 207).
In such a low-dimensional field-effect element having a dual-channel structure, transit electrons (hot carriers) accelerated by the drain voltage and raised to the energy level of the potential barrier between the two channels are real-space-transferred to the low-mobility channel sandwiched between the gate and the main high-mobility channel by applying gate voltage positively. The electrons transferred to the low-mobility channel travel at a reduced speed or stop. As a result, the planar density of the electrons passing through the high-mobility channel becomes equal to the result of subtracting the charge accumulated in the low-mobility channel from the total amount of charge induced by the gate voltage for satisfying charge neutrality condition, thereby producing the same effect as biasing the gate bias by the same amount in the negative direction. Therefore, owing to the resulting decrease of electrons in the high-mobility channel, the drain current declines substantially to give rise to negative differential resistance.
On the other hand, the present inventors previously proposed that for implementing this principle a dual-channel field-effect element structure using a quantum wire for the high-mobility channel is advantageous for suppressing dispersion of carriers in the channel (JP-A 2001-185559). Negative resistance is easier to induce in this element than in one using a quantum well, making it promising for use as an ultrahigh-speed logic element and the like.
However, it was difficult to actually make the lateral confinement size of the quantum wire smaller than around 100 nm and, therefore, while the power supply voltage at which negative differential resistance appeared (generally the drain voltage of a field-effect element) could be lowered compared with the prior art, it could still not be reduced adequately. Or to put it more exactly, there still was room for improvement.
An object of the present invention is to provide a negative resistance field-effect element that can achieve negative resistance at a lower drain voltage than conventionally while also ensuring a PVCR of adequate value.
The negative resistance field-effect element according to the present invention comprises: an InAlAs or AlGaAs barrier layer that, owing to being formed on an InP or GaAs substrate having an asymmetrical V-groove whose surface on one side is a (100) plane and surface on the other side is a (011) plane, has a trench, one of whose opposed lateral faces is a (111) A plane and the other of which is a (331) B plane; an InGaAs or GaAs quantum wire grown on a trench bottom surface of this barrier layer as a high-mobility channel having a relatively narrow energy band gap; an InAlAs or AlGaAs spacer layer grown on this quantum wire as a low-mobility channel having a relatively wide energy band gap; a source electrode and a drain electrode each in electrical continuity with the high-mobility channel through a contact layer and extending in a longitudinal direction of the quantum wire as spaced from each other; and a gate electrode provided between the source electrode and the drain electrode to face the low-mobility channel through an insulating layer or a Schottky junction.
Further, the present invention encompasses an element in which a delta-doped layer that lowers conduction band energy is provided locally within the low-mobility channel and the InAlAs or AlGaAs spacer layer constitutes a modulation-doped layer, and an element in which the contact layer contacted by the source electrode and drain electrode is a laminated structure of an n-type InAlAs layer, an n-type InGaAs layer, an n-type InGaAs layer and an n-type InAs layer.
Owing to the foregoing structure, lateral confinement size can, without restriction by the lithographic technology limit, be made 100 nm or less if required to thereby enable use of a very narrow-width quantum wire as the high-mobility channel and thereby achieve the object.